It is well known in the communication arts that a transmit (TX) buffer is required for both wired and wireless communications systems to interface the transmit path signal to the outside environment. In many cases, the transmit buffer is required to apply a variable gain to the transmit signal in order to increase or reduce the amplitude of the output signal. One such case occurs when the transmitted signal is part of an amplitude modulated communication system and the transmit buffer itself is used to implement the amplitude modulation function. The signal to noise ratio (SNR) requirements of such TX buffers in most systems are extremely strict, meaning that any amplitude control circuitry should contribute no more than negligible noise to the buffer output. The carrier leakage or reverse isolation (which can also be considered gain accuracy at low gain levels) of such transmit buffers is also an important concern. In addition, the current consumption requirements for these transmit buffers is limited such that any gain control scheme cannot ‘burn’ or waste current in order to meet the power consumption budget and the strict signal to noise requirements stated above.
There exist in the prior art multiple transmit chain architectures for transforming a digitally encoded bit stream into an RF modulated waveform at a power level suitable for transmission. The transmit power level for a cellular transceiver integrated circuit (IC) is typically around 3 dBm for interfacing with external power amplifiers (PAs). This output power level, however, is not constant in amplitude-modulated standards, such as EDGE, and must be controlled with appropriate variable-gain circuitry. Typical prior art architectures, such as single-sideband upconversion, perform digital-to-analog conversion on-chip and employ a variable gain pre-power amplifier (PPA) to transmit the required signal at the desired power level. In these architectures, the overall power consumption of the transmit chain, including all the D/A converters and variable gain buffer components, is at least 50 mW which is a relatively high amount of power. It is desirable to be able to reduce the power consumption of the transmit chain significantly.
In amplitude modulated communication systems, sigma-delta modulators can be used to amplitude modulate a transmit buffer that functions to provide digital to RF amplitude conversion (DRAC). The sigma-delta modulator is used to increase the resolution of the DRAC. The sigma-delta modulator “amplitude modulates” a carrier frequency signal, i.e. a clock signal resembling the carrier and having a frequency that is reflected by the period of the clock. A problem arises, however, when higher orders of MASH-structure sigma-delta modulators are used. Higher orders of sigma-delta modulator used to amplitude modulate a transmit buffer generates a positive offset that is added to the output signal. The size of the offset is dependent on the order of modulator used. The positive offset causes the output spectrum of the RF output signal to be distorted thus reducing the performance of the system whereby the system may now be out of the specifications of the particular communications standard.
Prior art solutions to this offset problem utilize a digital approach whereby the offset was measured and subtracted from the output signal. In systems where sigma-delta outputs directly drive analog transistors at RF frequencies, negative numbers do not exist in that portion of the circuit, and thus this solution will not work.
There is thus a long felt need for an amplitude modulator that (1) is capable of performing modulations without any offsets generated by the sigma-delta modulator; (2) does not require explicit digital subtraction; (3) is able to operate at RF frequencies of at least 1 GHz.